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VLSI Interview Questions and Answers

VLSI Interview Questions and Answers

VLSI Interview Questions and Answers

Q.1. Why transmission gate (TG) is called non-restoring circuit?

Answer: Transmission gate is a non-restoring circuit because if the input to transmission gate is a noisy or otherwise degraded signal, the output will receive the same noise.

Q.2. What do you mean by D register?

Answer: A collection of two or more D flip-flops sharing a common clock input is called a D register.

Q.3. Why pMOS transistors are wider than nMOS transistors?

Answer: pMOS transistors are often wider than NMOS transistors because holes move slowly than electrons, so the transistor has to be wider to deliver the same current.

Q.4. Enlist the types of design rules.

Answer: The design rules are usually described in two ways –

  • Micron rules, in which the layout constraints such as minimum feature sizes and minimum allowable feature separations are stated in terms of absolute dimensions in micrometers.
  • Lambda rules, which specify the layout constraints in terms of single parameter (λ) and thus allow linear, proportional scaling of all geometrical constraints.

Q.5. In how many ways digital VLSI design is portioned?

Answer: Digital VLSI design is often portioned into five levels of abstractions: architecture design, micro architecture design, logic design, circuit design and physical design.

Q.6. What is the role of compiler in MIPS processor?

Answer: A compiler translates a program from high level language source code into the appropriate machine language object code.

Q.7. What is the role of FSM in MIPS controller?

Answer: The controller contains a finite state machine (FSM) that generates multiplexer select signals and register enables to sequence the data path.

Q.8. What do you understand by driver and load?

Answer: The gate that charges or discharges a node is called the driver and the gates and wires being driven are called the load.

Q.9. What do you mean by slack? Also define positive slack and negative slack.

Answer: The “slack” is the difference between the required and arrival times. Positive slack means that the circuit meets timing. Negative slack means that the circuit is not fast enough.

Q.10. Define RC delay model.

Answer: The RC delay model approximates a switching transistor with an effective resistance and provides a way to estimate delay using arithmetic rather than differential equations.

Q.11. What is Miller effect?

Answer: If the inverter is biased in its linear region near VDD/2, the Cgd is multiplied by the large gain of the inverter. This is known as the Miller effect.

Q.12. Define activity factor (α). Why a clock has an activity factor of unity?

Answer: The activity factor is the probability that the circuit node transitions from 0 to 1, because that is the only time the circuit consumes power. A clock has an activity factor of unity because it rises and falls every cycle.

Q.13. What is the difference between interconnect and crosstalk?

Answer: The wires linking transistors together are called interconnect. When one wire switches, it tends to affect its neighboring through capacitive coupling, this effect is called crosstalk.

Q.14. Give the name of methods to cancel the effect of crosstalk.

Answer: There are three methods-

  • Staggered repeater.
  • Charge compensation.
  • Twisted differential signaling.

Q.15. How the limitations of a ROM based realization is overcome in a PLA based realization?

Answer: In a ROM, the encoder part is only programmable and use of ROMs to realize Boolean functions is wasteful in many situations because there is no cross-connect for a significant part. This wastage can be overcome by using programmable logic array (PLA), which requires much lesser chip area.

Q.16. What do you mean by latch-up problem?

Answer: Latch-up is defined as the generation of low-impedance path in CMOS chips between the power supply rails and the ground rails due to interconnection of parasitic pnp-npn bipolar transistor. These BJT form SCR with positive feedback and virtually short circuit, the power rail to ground thus causing excessive current flow and even permanent device damage.

Q.17. How the latch-up problem can be overcome?

Answer:  Latch-up problem can be overcome by –

  • Reduce the gains of BJT by lowering the minority carrier lifetime through gold doping of the substrate.
  • Use minimum area p-wells, so that the p-well photocurrent can be minimized during transient pulses.

Q.18. Why short-circuit power dissipation occurs?

Answer: Short-circuit power dissipation occurs because for a short time period both PMOS and NMOS transistors in the circuit may conduct simultaneously during the switching time. At this time, they form direct current path between the power supply and ground.

Q.19. What is the major difficulty in sequential circuit testing?

Answer: The major difficulty in sequential circuit testing is to determine the internal state of the circuit.

Q.20. State the D-algorithm.

Answer: The algorithm aims to find an assignment of input value that will allow detection of a particular internal fault by examining the output conditions. The D-algorithm provides a systematic means of assigning input values for that of particular design so that the discrepancy is driven to an output where it may be observed and thus detected.

Q.21. What are the objectives of Built-In self Test?

Answer:  The objectives of Built-In self Test are-

  • To reduce test pattern generation cost.
  • To reduce the volume of test data.
  • To reduce the test time.

Q.22. What are the factors that reduces the power dissipation?

Answer: The factors that reduces the power dissipation are-

  • Reduction of the power supply voltage VDD.
  • Reduction of the voltage swing at all nodes.
  • Reduction of the load capacitance.
  • Reduction of switching probability.

Q.23. A memory which stores the binary information in the form of charge in capacitor and lost the data when power supply is removed. Identify it.

Answer: DRAM.

Q.24. What do you understand by flash memory?

Answer: These devices use the same technology as EPROM but not only they are electrically programmed but also they can be erased electrically in very short time.

The great advantage of all these ROM devices is that they are non-volatile; it means that when the power is switched off, the stored data is not lost.

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